1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device and, in particular, to a semiconductor device having an SOI structure and a method for manufacturing the same.
2. Background Art
The SOI (Silicon On Insulator) substrate of transistors having an SOI structure consists of a multilayered stack of an underlying silicon substrate, a buried insulator, and an SOI layer. A gate electrode is formed on top of a gate insulator on the SOI substrate. The SOI layer is separated into active areas by a partial isolation insulator. The partial isolation insulator is formed by filling a trench in the SOI layer with an insulator such as an oxide. The trench is formed down to a depth such that it does not completely penetrate through the SOI layer. The portion of SOI layer left under the partial isolation insulator acts as a well.
A portion of the SOI layer under the gate electrode is a channel region. Impurity diffused layers (extension and source/drain) are formed on both sides of the channel region. A body potential fixing region for fixing a body potential is provided on the opposite side of the partial isolation insulator from the channel region. The channel region and the body potential fixing regions are electrically interconnected through the well.
For forming the body potential fixing region and the impurity diffused regions on both sides of the gate electrode, ions of opposite types are implanted respectively. During the ion implantation of the source/drain, therefore, the body potential fixing region is masked with a resist; during the ion implantation of the body potential fixing region, the impurity diffused layer is masked with a resist.
The gate electrode is separated from the body potential fixing region by the partial isolation insulator. When ion implantation is performed, typically a resist mask is not provided on the partial isolation insulator. During such ion implantation, ions are also implanted into the partial isolation insulator.
In SOI semiconductor devices, the partial isolation insulator is very thin. Accordingly, when ions are implanted into the partial isolation insulator without a mask, some of the ions may penetrate through the partial isolation insulator into the well under it. If ions are implanted into the well, the resistance of the well, from the body potential fixing region to the channel region, may increase and thus isolation characteristics can degrade.
To prevent this problem, an approach has been proposed in which a resist mask used during source/drain implantation is provided so as to cover the partial isolation insulator between the gate electrode and the body potential fixing region as well as the body potential fixing region, and the ion implantation is performed with the resist mask to prevent undesired impurity from penetrating into the well (for example see Japanese Patent Laid-Open No. 2002-208705).
Especially during ion implantation of the impurity diffused layers (extension and source/drain), ions must be precisely implanted in proper positions on both sides of the gate electrode. Therefore, when a resist mask is provided on the partial isolation insulator as stated above, the resist mask must be precisely aligned with the gate electrode. However, precise alignment of the resist is difficult to achieve. If the resist mask cannot precisely be formed and unnecessarily overlaps the gate electrode, sufficient ions cannot be implanted in proper positions.